The present invention relates to nonvolatile semiconductor memory devices and particularly relates to area reduction of a nonvolatile semiconductor memory device including a nonvolatile memory element fabricated by a standard CMOS process.
Recently, a desire is grown that information typified by contents' encryption key is incorporated in a system LSI fabricated by a standard CMOS process. Utilization of a metal fuse for the incorporation has been examined, but apprehension about information leakage through analysis still remains. To tackle this problem, incorporation of a low-cost rewriteable nonvolatile memory device may be considered.
In the case where a nonvolatile semiconductor memory device, such as a flash memory or the like is incorporated in a system LSI, a dedicated process is required in addition to the standard CMOS process to thus increase the process cost, disabling application to an advanced process. In view of this, a low-cost nonvolatile semiconductor memory device is demanded which is capable of being embedded in an LSI fabricated by an advanced standard CMOS process.
To meet the above demand, a CMOS nonvolatile memory has been proposed which includes a floating gate formed of a single NMOS gate and two PMOS gates capable of being embedded in an LSI fabricated by the standard CMOS process and which uses a first PMOS diffusion layer region as a control gate during a programming operation and a read operation while using a second PMOS diffusion layer region during an erase operation (see Richard J. McPartland, et al., “1.25 Volt, Low Cost, Embedded FLASH Memory for Low Density Applications,” 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp. 158-161).
FIG. 22 is a circuit diagram of a conventional nonvolatile memory element composed of one NMOS transistor and two PMOS transistors. FIG. 23 is a sectional view of the conventional nonvolatile memory element shown in FIG. 22.
In FIG. 22, reference numeral 1 denotes a control gate transistor (PMOS transistor), 2 denotes an erase gate transistor (PMOS transistor), 3 denotes a read transistor (NMOS transistor), 4 denotes a control gate (CG), 5 denotes an erase gate (EG), 6 denotes a drain terminal of the NMOS transistor, 7 denotes a source terminal of the NMOS transistor, and 8 denotes a P-type silicon substrate terminal. Reference numeral 9 denotes a floating gate (FG) connecting the gates of the PMOS transistors 1, 2 and the gate of the NMOS transistor 3.
As shown in FIG. 23, the NMOS transistor 3 is formed on a P-type silicon substrate 10 and includes N-type conductive regions and a gate electrode. The PMOS transistors 1, 2 are formed on N-type wells 11, 12, respectively, in the P-type silicon substrate 10 and each includes P-type conductive regions and a gate electrode. The floating gate (FG) 9 connects the gate electrode of the NMOS transistor 3 and the gate electrodes of the PMOS transistors 1, 2. A write operation, a read operation, and an erase operation of carriers to or from the floating gate (FG) are performed by applying predetermined voltages to the respective terminals.
Referring to a core structure of the nonvolatile semiconductor memory device including a nonvolatile memory element capable of being fabricated by the standard CMOS process, a line configuration using a fuse is employed in which lines, of which number is equal to the number of bit cells, are serially connected, wherein each bit cell includes a sense amplifier, a latch circuit, and a shift register (see Japanese Patent Application Laid Open unexamined Publication No. 2005-267794).
The aforementioned nonvolatile semiconductor memory device capable of being fabricated by the standard CMOS process, however, assumes employment of a fuse, which has small capacity, and therefore, the line configuration should have been employed in which lines, of which number is equal to the number of bit cells, are serially connected, wherein each bit cell includes a sense amplifier, a latch circuit, and a shift register. Accordingly, implementation of a nonvolatile memory core having middle capacity of several kilobits results in an increase in core area.